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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 12-bit serial input multiplying cmos d/a converter dac8043 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram pin connections 8-pin epoxy dip (p-suffix) 8-pin cerdip (z-suffix) 16-lead wide-body sol (s-suffix) 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 top view (not to scale) dac8043 nc = no connect clk v dd n.c. n.c. n.c. ld sri n.c. n.c. n.c. v ref r fb i out gnd gnd n.c. general description the dac8043 is a high accuracy 12-bit cmos multiplying dac in a space-saving 8-pin mini-dip package. featuring serial data input, double buffering, and excellent analog performance, the dac8043 is ideal for applications where pc board space is at a premium. also, improved linearity and gain error performance permit red uced parts count through the elimination of trimming components. separate input clock and load dac control lines allow full user control of data loading and analog output. the circuit consists of a 12-bit serial-in, parallel-out shift regis- ter, a 12-bit dac register, a 12-bit cmos dac, and control logic. serial data is clocked into the input register on the rising edge of the clock pulse. when the new data word has been clocked in, it is loaded into the dac register with the ld input pin. data in the dac register is converted to an output current by the d/a converter. the dac8043s fast interface timing may reduce timing design considerations while minimizing microprocessor wait states. for applications requiring an asynchronous clear function or more versatile microprocessor interface logic, refer to the pm-7543. operating from a single +5 v power supply, the dac8043 is the ideal low power, small size, high performance solution to many application problems. it is available in plastic and cerdip packages that are compatible with auto-insertion equipment. features 12-bit accuracy in an 8-pin mini-dip fast serial data input double data buffers low 6 1/2 lsb max inl and dnl max gain error: 6 1 lsb low 5 ppm/ 8 c max tempco esd resistant low cost available in die form applications autocalibration systems process control and industrial automation programmable amplifiers and attenuators digitally-controlled filters
rev. c C2C dac8043Cspecifications electrical characteristics dac8043 parameter symbol conditions min typ max units static accuracy resolution n 12 bits nonlinearity inl dac8043a/e/g 1/2 lsb (note 1) dac8043f 1 lsb differential nonlinearity dnl dac8043a/e 1/2 lsb (note 2) dac8043f/g 1 lsb gain error g fse t a = +25 c (note 3) dac8043a/e 1 lsb dac8043f/g 2 lsb t a = full temperature range all grades 2 lsb gain tempco ( d gain/ d temp) tc gfs 5 ppm/ c (note 5) power supply rejection ratio psrr d v dd = 5% 0.0006 0.002 %/% ( d gain/ d v dd ) output leakage current i lkg t a = +25 c 5na (note 4) t a = full temperature range dac8043a 100 na dac8043e/f/g 25 na zero scale error i zse t a = +25 c 0.03 lsb (notes 7, 12) t a = full temperature range dac8043a 0.61 lsb dac8043e/f/g 0.15 lsb input resistance (note 8) r in 71115k w ac performance output current settling time t s t a = +25 c 0.25 1 m s (notes 5, 6) v ref = 0 v digital to analog i out load = 100 w glitch energy q c ext = 13 pf 2 20 nvs (note 5, 10) dac register loaded alternately with all 0s and all 1s feedthrough error v ref = 20 v p-p @ f = 10 khz (v ref to i out ) ft digital input = 0000 0000 0000 0.7 1 mv p-p (note 5, 11) t a = +25 c total harmonic distortion thd v ref = 6 v rms @ 1 khz C85 db (note 5) dac register loaded with all 1s output noise voltage density e n 10 hz to 100 khz between r fb and i out 17 nv/ ? hz (note 5, 13) digital inputs digital input high v in 2.4 v digital input low v il 0.8 v input leakage current i il v in = 0 v to +5 v 1 m a (note 9) input capacitance c in v in = 0 v 8 pf (note 5, 11) analog outputs output capacitance c out digital inputs = v ih 110 pf (note 5) digital inputs = v il 80 pf (@ v dd = +5 v; v ref = +10 v; i out = gnd = 0 v; t a = full temperature range specified under absolute maximum ratings unless otherwise noted).
dac8043 parameter symbol conditions min typ max units timing characteristics (notes 5, 14) data setup time t ds t a = full temperature range 40 ns data hold time t dh t a = full temperature range 80 ns clock pulse width high t ch t a = full temperature range 90 ns clock pulse width low t cl t a = full temperature range 120 ns load pulse width t ld t a = full temperature range 120 ns lsb clock into input register to load dac register time t asb t a = full temperature range 0 ns power supply supply voltage v dd 4.75 5 5.25 v supply current i dd digital inputs = v ih or v il 500 m a max digital inputs = 0 v or v dd 100 m a max C3C rev. c notes 1 1 1/2 lsb = 0.012% of full scale. 1 2 all grades are monotonic to 12-bits over temperature. 1 3 using internal feedback resistor. 1 4 applies to i out ; all digital inputs = 0 v. 1 5 guaranteed by design and not tested. 1 6 i out load = 100 w , c ext = 13 pf, digital input = 0 v to v dd or v dd to 0 v. extrapolated to 1/2 lsb; t s = propagation delay (t pd ) + 9 t where t = measured time constant of the final rc decay. 1 7 v ref = +10 v, all digital inputs = 0 v. 1 8 absolute temperature coefficient is less than +300 ppm/ c. 1 9 digital inputs are cmos gates; i in is typically 1 na at +25 c. 10 v ref = 0 v, all digital inputs = 0 v to v dd or v dd to 0 v. 11 all digit inputs = 0 v. 12 calculated from worst case r ref : i zse (in lsbs) = (r ref i lkg 4096)/v ref . 13 calculations from en = ? 4k trb where: k = boltzmann constant, j/ k, r = resistance, w , t = resistor temperature, k, b = bandwidth, hz. 14 tested at v in = 0 v or v dd . specifications subject to change without notice. absolute maximum ratings (t a = +25 c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+17 v v ref to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 v v rfb to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 v digital input voltage range . . . . . . . . . . . . . . . C0.3 v to v dd output voltage (pin 3) . . . . . . . . . . . . . . . . . . . C0.3 v to v dd operating temperature range az versions . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c ez/fz/fp versions . . . . . . . . . . . . . . . . . . . C40 c to +85 c gp version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c storage temperature . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 60 sec) . . . . . . . . . . . . . +300 c package type u ja * u jc units 8-pin hermetic dip (z) 134 12 c/w 8-pin plastic dip (p) 96 37 c/w * u ja is specified for worst case mounting conditions, i. e., u ja is specified for device in socket for cerdip and p-dip packages. caution 1. do not apply voltages higher than v dd or less than gnd po- tential on any terminal except v ref (pin 1) and r fb (pin 2). 2. the digital control inputs are zener-protected; however, per- manent damage may occur on unprotected units from high energy electrostatic fields. keep units in conductive foam at all times until ready to use. 3. use proper antistatic handling procedures. 4. absolute maximum ratings apply to both packaged devices and dice. stresses above those listed under absolute maxi- mum ratings may cause permanent damage to the device. ordering guide 1 relative temperature package model accuracy range option dac8043az 2 1/2 lsb C55 c to +125 c 8-pin cerdip dac8043az/883 2 1/2 lsb C55 c to +125 c 8-pin cerdip dac8043ez 1/2 lsb C40 c to +125 c 8-pin cerdip dac8043fs 1 lsb C40 c to +85 c 16-lead (wide) sol dac8043fz 1 lsb C40 c to +85 c 8-pin cerdip dac8043fp 1 lsb C40 c to +85 c 8-pin epoxy dip dac8043gp 1/2 lsb 0 c to +70 c 8-pin epoxy dip dac8043hp 1 lsb 0 c to +70 c 8-pin epoxy dip notes 1 all commercial and industrial temperature range parts are available with burn-in. 2 for devices processed in total compliance to mil-std-883, add/883 after part number. consult factory for 883 data sheet. dac8043
dac8043 C4C rev. c wafer test limits @ v dd = + 5 v, v ref = +10 v; i out = gnd = 0 v, t a = +25 8 c. dac8043gbc parameter symbol conditions limit units static accuracy resolution n 12 bits min integral nonlinearity inl 1 lsb max differential nonlinearity dnl 1 lsb max gain error g fse using internal feedback resistor 2 lsb max power supply rejection ratio psrr d v dd = 5% 0.002 %/% max output leakage current (i out )i lkg digital inputs = v il 5 na max reference input input resistance r in 7/15 k w min/max digital inputs digital input high v ih 2.4 v min digital input low v il 0.8 v max input leakage current i il v in = 0 v to v dd 1 m a max power supply supply current i dd digital inputs = v in or v il 500 m a max digital inputs = 0 v or v dd 100 m a max note electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. dice characteristics die size 0.116 0.109 inch, 12,644 sq. mils (2.95 2.77 mm, 8.17 sq. mm) 1. v ref 2. r fb 3. i out 4. gnd 5. ld 6. sri 7. clk 8. v dd substate (die backside) is internally connected to v dd . warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the dac8043 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
dac8043 C5C rev. c typical performance characteristics supply current vs. logic input voltage linearity error vs. digital code linearity error vs. reference voltage gain vs. frequency (output amplifier: op42) logic threshold voltage vs. supply voltage total harmonic distortion vs. frequency (multiplying mode) dnl error vs. reference voltage
dac8043 C6C rev. c figure 1. digital input protection the digital circuitry forms an interface in which serial data can be loaded under microprocessor control into a 12-bit shift regis- ter and then transferred, in parallel, to the 12-bit dac register. a simplified circuit of the dac8043 is shown in figure 2. an inverted r-2r ladder network consisting of silicon-chrome, highly-stable (+50 ppm/ c) thin-film resistors, and twelve pairs of nmos current-steering switches. these switches steer binarily weighted currents into either i out or gnd; this yields a constant current in each ladder leg, regard- less of digital input code. this constant current results in a con- stant input resistance at v ref equal to r. the v ref input may be driven by any reference voltage or current, ac or dc that is within the limits stated in the absolute maximum ratings. the twelve output current-steering nmos fet switches are in series with each r-2r resistor, they can introduce bit errors if all are of the same r on resistance value. they were designed such that the switch on resistance be binarily scaled so that the voltage drop across each switch remains constant. if, for ex- ample, switch 1 of figure 2 was designed with an on resis- tance of 10 w , switch 2 for 20 w , etc., a constant 5 mv drop will then be maintained across each switch. write cycle timing diagram parameter definitions integral nonlinearity (inl) this is the single most important dac specification. adi mea- sures inl as the maximum deviation of the analog output (from the ideal) from a straight line drawn between the end points. it is expressed as a percent of full-scale range or in terms of lsbs. refer to pmi 1988 data book section 11 for additional digital- to-analog converter definitions. interface logic information the dac8043 has been designed for ease of operation. the timing diagram illustrates the input register loading sequence. note that the most significant bit (msb) is loaded first. once the input register is full, the data is transferred to the dac register by taking ld momentarily low. digital section the dac8043s digital inputs, sri, ld , and clk, are ttl compatible. the input voltage levels affect the amount of cur- rent drawn from the supply; peak supply current occurs as the digital input (v in ) passes through the transition region. see the supply current vs. logic input voltage graph located under the typical performance characteristics curves. maintaining the digi- tal input voltage levels as close as possible to the supplies, v dd and gnd, minimizes supply current consumption. the dac8043s digital inputs have been designed with esd re- sistance incorporated through careful layout and the inclusion of input protection circuitry. figure 1 shows the input protection diodes and series resistor; this input structure is duplicated on each digital input. high voltage static charges applied to the in- puts are shunted to the supply and ground rails through forward biased diodes. these protection diodes were designed to clamp the inputs to well below dangerous levels during static discharge conditions. general circuit information the dac8043 is a 12-bit multiplying d/a converter with a very low temperature coefficient. it contains an r-2r resistor ladder network, data input and control logic, and two data registers.
dac8043 C7C rev. c dynamic performance output impedance the dac8043s output resistance, as in the case of the output capacitance, varies with the digital input code. this resistance, looking back into the i out terminal, may be between 10 k w (the feedback resistor alone when all digital inputs are low) and 7.5 k w (the feedback resistor in parallel with approximate 30 k w of the r-2r ladder network resistance when any single bit logic is high). static accuracy and dynamic performance will be af- fected by these variations. this variation is best illustrated by using the circuit of figure 4 and the equation: v error = v os 1 + r fb r o ? ? ? ? where r o is a function of the digital code, and: r o = 10 k w for more than four bits of logic 1. r o = 30 k w for any single bit of logic 1. therefore, the offset gain varies as follows: at code 0011 1111 1111, v error 1 = v os 1 + 10 k w 10 k w ? ? ? ? = 2 v os at code 0100 0000 0000, v error 2 = v os 1 + 10 k w 30 k w ? ? ? ? = 4/3 v os the error difference is 2/3 v os . since one lsb has a weight (for v ref = +10 v) of 2.4 mv for the dac8043, it is clearly important that v os be minimized, either using the amplifiers nulling pins, an external nulling net- work, or by selection of an amplifier with inherently low v os . amplifiers with sufficiently low v os include adis op77, op07, op27, and op42. figure 4. simplified circuit to further insure accuracy across the full temperature range, permanently on mos switches were included in series with the feedback resistor and the r-2r ladders terminating resistor. the simplified dac circuit, figure 2, shows the location of the series switches. these series switches are equivalently scaled to two times switch 1 (msb) and to switch 12 (lsb) respec- tively to maintain constant relative voltage drops with varying temperature. during any testing of the resistor ladder or r feedback (such as incoming inspection), v dd must be present to turn on these series switches. figure 2. simplified dac circuit equivalent circuit analysis figure 3 shows an equivalent analog circuit for the dac8043. the (d v ref )/r current source is code dependent and is the current generated by the dac. the current source i lkg consists of surface and junction leakages and doubles approximately ev- ery 10 c. c out is the output capacitance; it is the result of the n-channel mos switches and varies from 80 pf to 110 pf depending on the digital input code. r o is the equivalent output resistance that also varies with digital input code. r is the nomi- nal r-2r resistor ladder resistance. figure 3. equivalent analog circuit
dac8043 C8C rev. c figure 6. unipolar operation with fast op amp and gain error trimming (2-quadrant) the analog output is shown in table i. the limiting parameters for the v ref range are the maximum input voltage range of the op amp or 25 v, whichever is lowest. gain error may be trimmed by adjusting r 1 as shown in figure 6. the dac register must first be loaded with all 1s. r 1 may then be adjusted until v out = Cv ref (4095/4096). in the case of an adjustable v ref , r 1 and r 2 may be omitted, with v ref ad- justed to yield the desired full-scale output. in most applications the dac8043s negligible zero scale error and very low gain error permit the elimination of the trimming components (r 1 and the external r 2 ) without adverse effects on circuit performance. the gain and phase stability of the output amplifier, board lay- out, and power supply decoupling will all affect the dynamic performance. the use of a small compensation capacitor may be required when high-speed operational amplifiers are used. it may be connected across the amplifiers feedback resistor to provide the necessary phase compensation to critically damp the output. the dac8043s output capacitance and the r fb resis- tor form a pole that must be outside the amplifiers unity gain crossover frequency. the considerations when using high-speed amplifiers are: 1. phase compensation (see figures 5 and 6). 2. power supply decoupling at the device socket and use of proper grounding techniques. applications information application tips in most applications, linearity depends upon the potential of i out and gnd (pins 3 and 4) being exactly equal to each other. in most applications, the dac is connected to an external op amp with its noninverting input tied to ground (see figures 5 and 6). the amplifier selected should have a low input bias cur- rent and low drift over temperature. the amplifiers input offset voltage should be nulled to less than +200 m v (less than 10% of 1 lsb). the operational amplifiers noninverting input should have a minimum resistance connection to ground; the usual bias cur- rent compensation resistor should not be used. this resistor can cause a variable offset voltage appearing as a varying output er- ror. all grounded pins should tie to a single common ground point, avoiding ground loops. the v dd power supply should have a low noise level with no transients greater than +17 v. unipolar operation (2-quadrant) the circuit shown in figures 5 and 6 may be used with an ac or dc reference voltage. the circuits output will range between 0 v and approximately Cv ref (4095/4096) depending upon the digital input code. the relationship between the digital input and figure 5. unipolar operation with high accuracy op amp (2-quadrant) table i. unipolar code table digital input nominal analog output msb lsb (v out as shown in figures 5 and 6) 1111 1111 1111 Cv ref 4095 4096 ? ? ? ? 1000 0000 0001 Cv ref 2049 4096 ? ? ? ? 1000 0000 0000 Cv ref 2048 4096 ? ? ? ? = C v ref 2 0111 1111 1111 Cv ref 2047 4096 ? ? ? ? 0000 0000 0001 Cv ref 1 4096 ? ? ? ? 0000 0000 0000 Cv ref 0 4096 ? ? ? ? = 0 notes 1 nominal full scale for the circuits of figures 5 and 6 is given by fs = Cv ref 4095 4096 ? ? ? ? 2 nominal lsb magnitude for the circuits of figures 5 and 6 is given by lsb = v ref 1 4096 ? ? ? ? or v ref (2 Cn ).
dac8043 C9C rev. c table ii. bipolar (offset binary) code table digital input nominal analog output msb lsb (v out as shown in figure 7) 1111 1111 1111 +v ref 2047 2048 ? ? ? ? 1000 0000 0001 +v ref 1 2048 ? ? ? ? 1000 0000 0000 0 0111 1111 1111 Cv ref 1 2048 ? ? ? ? 0000 0000 0001 Cv ref 2047 2048 ? ? ? ? 0000 0000 0000 Cv ref 2048 2048 ? ? ? ? notes 1 nominal full scale for the circuit of figure 7 is given by fs = v ref 2047 2048 ? ? ? . 2 nominal lsb magnitude for the circuit of figure 7 is given by lsb = v ref 1 2048 ? ? ? . resistors r 3 , r 4 , and r 5 must be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient matching. mismatching between r 3 and r 4 causes offset and full scale errors while an r 5 to r 4 and r 3 mismatch will result in full-scale error. calibration is performed by loading the dac register with 1000 0000 0000 and adjusting r 1 until v out = 0 v. r 1 and r 2 may be omitted, adjusting the ratio of r 3 to r 4 to yield v out = 0 v. full scale can be adjusted by loading the dac register with 1111 1111 1111 and either adjusting the amplitude of v ref or the value of r 5 until the desired v out is achieved. analog/digital division the transfer function for the dac8043 connected in the multi- plying mode as shown in figures 5, 6 and 7 is: v o = Cv in a 1 2 1 + a 2 2 2 + a 3 2 3 + ... a 12 2 12 ? ? ? ? where a x assumes a value of 1 for an on bit and 0 for an off bit. the transfer function is modified when the dac is connected in the feedback of an operational amplifier as shown in figure 8 and becomes: v o = v in a 1 2 1 + a 2 2 2 + a 3 2 3 + ... a 12 2 4 ? ? ? ? ? ? the above transfer function is the division of an analog voltage (v ref ) by a digital word. the amplifier goes to the rails with all bits off since division by zero is infinity. with all bits on, the gain is 1 ( 1 lsb). the gain becomes 4096 with the lsb, bit 12 on. figure 7. bipolar operation (4-quadrant, offset binary) bipolar operation (4-quadrant) figure 7 details a suggested circuit for bipolar, or offset binary operation. table ii shows the digital input to analog output re- lationship. the circuit uses offset binary coding. twos comple- ment code can be converted to offset binary by software inversion of the msb or by the addition of an external inverter to the msb input.
dac8043 C10C rev. c figure 8. analog/digital divider interfacing to the mc6800 as shown in figure 9, the dac8043 may be interfaced to the 6800 by successively executing memory write instructions while manipulating the data between writes, so that each write presents the next bit. in this example the most significant bits are found in memory location 0000 and 0001. the four msbs are found in the lower half of 0000, the eight lsbs in 0001. the data is taken from the db 7 line. the serial data loading is triggered by the clk pulse which is asserted by a decoded memory write to memory location 2000, r/ w , and f 2. a write to address 4000 transfers data from input register to dac register. figure 9. dac8043Cmc6800 interface dac8043 interface to the 8085 the dac8043s interface to the 8085 microprocessor is shown in figure 10. note that the microprocessors sod line is used to present data serially to the dac. data is clocked into the dac8043 by executing memory write instructions. the clock input is generated by decoding address 8000 and wr. data is loaded into the dac register with a memory write instruction to address a000. serial data supplied to the dac8043 must be present in the right justified format in registers h and l of the microprocessor. figure 10. dac8043-8085 interface dac8043 to 68000 interfacing the dac8043 interfacing to the 68000 microprocessor is shown in figure 11. again, serial data to the dac is taken from one of the microprocessors data bus lines. figure 11. dac8043C68000 m p interface
C11C
000000000 printed in u.s.a. C12C

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